A New and Fast Approach to Very Large Scale Integrated Sequential Circuit Test Generation
Operations Research · 1997 · Volume 45 · Issue 6
Abstract
We present a new approach to automatic test pattern generation for very large scale integrated sequential circuit testing. This approach is more efficient than past test generation methods, since it exploits knowledge of potential circuit defects. Our method motivates a new combinatorial optimization problem, the Tour Covering Problem . We develop heuristics to solve this optimization problem, then apply these heuristics as new test generation procedures. An empirical study comparing our heuristics to existing methods demonstrates the superiority of our approach, since our approach decreases the number of input vectors required for the test, translating into a reduction in the time and money required for testing sequential circuits.
Keywords
industry, computer electronic, semiconductor manufacturing, manufacturing performance/productivity, improved quality control by effective testing, programming integer heuristic, heuristic approach for the tour cover problem
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